00:00 intro 
00:56 z80 
04:54 Submitted to TT07 
06:52 NMOS 
08:22 dynamic memory 
10:28 z80 was everything in one chip 
12:00 hand layout 
14:10 most widely used CPU in the 80s 
17:27 Tiny Tapeout compromise 
18:56 voltage compatibility 
19:58 Fits in 4 TT tiles 
21:09 comparison table 
22:47 What is Tiny Tapeout 
24:28 next steps 
26:29 bond pads 
28:09 multicore z80 
28:59 pricing 
29:30 why not use an FPGA?
30:30 what to use for 1.8v core? 
31:02 all the classics? 
31:53 important to preserve the old chips 
32:50 the plan 
35:19 how can you help?

using X-rays to make 3D images of chips with Tomas Aidukas

Jorge Marín - DC / DC converter design and the IEEE chipathon

In this interview Arya Reais-Parsi talks about:

00:45? FPGA design is for a course
01:50? difference between other open FPGA fabrics
02:50? FPGAs as accelerators
04:27? their FPGA structure
06:30? how did they target ASIC?
09:27? GDS view of the FPGA structure
11:40? custom cells for FPGAs
14:40? making lab notes
16:00? how does actually taping something out change the feeling of the work?
17:10? how will this shuttle program changes things going forwards?
22:40? future of ASIC with more open tooling and access
24:30? toolchain for their FPGA: yosys & nextpnr

Their group's application is here:
https://github.com/ucb-cs250/caravel_...

00:00 Introducing  Dan Rodrigues
01:15 Dan was on the first shuttle
02:30 Converting an FPGA project to an ASIC
03:17 How long it took to prepare his submission?
05:17 What kind of config changes were required?
07:50 VDP-lite - wishbone peripheral that can generate sprites and put out on VGA: https://github.com/dan-rodrigues/caravel_vdp_lite 
08:45 No framebuffer
11:20 How many flip flops were required?
12:37 A look at the GDS
14:10 Framebuffer vs racing the beam
16:28 How does the wishbone part work? How can VDP-lite be controlled?
18:10 Do you have projects planned to run on the hardware
19:06 Sam Littlewood’s PCB: https://github.com/samlittlewood/caravel_carrier
25:44 Diadatp made a PR on VGA clock demo for realtime verilator rendering
26:00 Caravel test structure 
27:06 Icestation32: https://github.com/dan-rodrigues/icestation-32
28:31 Recommendations from Dan about how to learn more about retro gaming
30:12 Ultimate Gameboy talk: https://www.youtube.com/watch?v=HyzD8pNlpwI

One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1.

In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them.

00:00? introduction
01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...?
02:18? Questions from Niklas - time it takes, what's frustrating, fun?
05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel.
07:20? Question from Pepijn - what would you need to change to alter the PLL?
08:44? PLL overview
10:00? Lakshmi's design: Frequency divider
12:22? Phase frequency detector
13:32? Charge pump
14:37? Voltage controlled oscillator
16:40? combined designs with Diego Hernando
17:10? putting into the Caravel wrapper, adding space
18:56? Question from Brady - why design an integrated loop filter
20:01? Questions from Top - are there schematics? Process corners and ngspice convergence
22:05? Question from Steven: post silicon testing

Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/?
Repo: https://github.com/lakshmi-sathi/avsd...

In this interview with Matt Guthaus, we talk about:

• Recap - what is OpenRAM
• Why do we need a memory compiler like OpenRAM?
• 3 phases of OpenRAM development
• What’s changed since FOSSi dialup
• MPW2 tapeout of OpenRAM
• Test modes
• What was hard about MPW2
• DRC issues
• Status of OpenLANE support for OpenRAM
• Future plans for OpenRAM
• Access to resistive RAM, hopefully for MPW4

00:00 Introducing Thomas Parry
00:36 Project is an amateur satellite transceiver
01:02 Thomas wanted a challenging project
01:17 His background
01:50 Working for SystematIC Design in Delft doing analogue chip design
02:29 Design split into 2 repositories, see links below
03:50 Day to day work with Cadence and MentorGraphics industry standard tools
04:25 Pay money to reduce risk - no one to shout at
05:42 Previous interviews with Diego & Lakshmi
06:04 His design process is similar
06:57 Using Klayout for layout
07:15 Using OpenLANE for a small part of the design
08:35 Still uses Magic for extraction of circuit
08:52 Nice structure in his repository
10:24 Overview of the structure of a transceiver
12:20 Difference of the visual appearance of digital vs analogue layout
12:46 Taking a look at the GDS
13:30 Control signals
13:46 Digital section - fractional N divider for the PLL
14:29 9x9 array charge pump output
15:30 VCO - do they always look like bathroom tiles?
15:55 4 inverting amplifiers arranged in a ring
16:35 Created MOSFETs with the generator in Magic, then exported into Klayout
17:08 8x4 blocks of output drivers
17:40 Compensation filter for the PLL is off-chip
18:50 Characterise bandgap in a thermal chamber
19:30 Bandgap references replicated 3 times for different measurement options
20:15 Lovely routing!
21:08 Drawn by hand…
21:14 Ruby & Python scripting for Klayout
21:45 Efabless are working to integrate Klayout more tightly into OpenLANE
22:54 Terminology corner: Corner!
24:04 Typical Typical
25:26 How to get the RF signals in and out of Caravel padring?
26:35 WLCSP
27:20 Currently IO cells are digital
27:44 First 8 pins can be switched to analogue, but not ideal for high frequency
28:16 Power amplification
28:58 What are the next steps? Complete the TX chain
30:20 How to get started with analogue design?
32:02 Python binding for spice: https://pypi.org/project/PySpice/ 
33:02 Books by Behzad Razavi are recommended.

Design repo: https://github.com/yrrapt/amsat_txrx_ic 
Shuttle application repo: https://github.com/yrrapt/caravel_amsat_txrx_ic 

Connect with Thomas here: https://www.linkedin.com/in/thomas-parry-60419468/

00:12 Tim Edwards introduction
01:00 next steps after submission before files sent to Skywater
02:00 infrastructure - getting all the latest from everyone's repositories
03:05 size of the repos can be a problem
03:41 revolutionary part of this run is that everything is Open Source down to the GDS
04:51 Open Source PDK is what makes it possible to do this for eFabless
05:12 Why didn't we submit the source rather than the final GDS?
09:42 Got all the GDS2 files from the repos, what's the next step?
10:00 3 scripts, 1st applies a user id
13:04 2nd script does fill generation
16:14 3rd script does compositing
19:39 DRC count for Caravel
23:00 lots of people have helped make this happen
23:50 biggest project at eFabless
24:00 When do you think the files will get sent to Skywater?

Open Source VLSI tools: http://opencircuitdesign.com/
eFabless: https://efabless.com/company

Tom Spyrou is a long time EDA developer who has worked at large and small companies.

• In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation.
• He was the original architect of PrimeTime STA algorithm.
• Manager of Cadence Common timing Engine and precursor to Open Access
• Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

Since 2019 he has been the Chief Architect and Technical Project Manager of OpenROAD since 2019.

We have just heard the announcement that OpenLANE will become the defacto flow for OpenROAD.

So I felt very lucky that he was willing to spend half an hour talking to us about a wide range of topics including:

• OpenROAD history & context
• What is the aim of OpenROAD
• State of the art in industry vs research
• Training the next generation of EDA developers
• Shortage of EDA developers
• Use of other PDKs besides Sky130
• Value of open source PDKs
• Roadmap and improvements: PPA
• Machine learning additions for OpenROAD
• Cloud scale compute for OpenROAD
• OpenLANE and OpenROAD collaboration announcement
• Future hopes